Transition Coupling Circuitry for Memory Applications

A method for manufacturing an integrated circuit, the method comprising:

• fabricating memory circuitry having a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair;
• fabricating first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry;
• and
• fabricating second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs;
• wherein the first bitline pair and the second bitline pair are on a lower metal layer and the jumper bitline pairs are on a higher metal layer.

An integrated circuit, comprising:

• memory circuitry having a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair, wherein the first bitline pair is separate from the second bitline pair;
• first transition coupling circuitry for accessing the first array of bitcells with the first bitline pair and a jumper bitline pair, wherein the first bitline pair is disposed in a first metal layer;
• and
• second transition coupling circuitry for accessing the second array of bitcells with the second bitline pair and the jumper bitline pair, wherein the second bitline pair is disposed in the first metal layer, and wherein the jumper bitline pair is disposed in a second metal layer that is different than the first metal layer.