Semiconductor storage element, semiconductor storage device, and semiconductor system
AssigneeSony Semiconductor Solutions Corporation
InventorMASANORI TSUKAMOTO
Life of this patent
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Abstract
[Object] To provide a semiconductor storage element that has a more reduced planar area. [Solution] A semiconductor storage element including: a memory cell transistor including a gate insulator film at least partially including ferroelectric material; and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.
Claims13
A semiconductor storage element comprising:
- a memory cell transistor including a gate insulator film at least partially including ferroelectric material;
- and
- a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.
A semiconductor storage device comprising:
- a plurality of semiconductor storage elements arranged in a matrix, the plurality of semiconductor storage elements each including
- a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and
- a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer.
A semiconductor system comprising:
- a storage device including a plurality of semiconductor storage elements arranged in a matrix and each including a memory cell transistor including a gate insulator film at least partially including ferroelectric material, and a selection transistor provided in such a manner that one of a source or a drain is connected with a gate electrode of the memory cell transistor via a connection layer, and a gate insulator film faces the gate insulator film of the memory cell transistor in a layer stack direction across the connection layer;
- and
- an arithmetic device connected with the storage device,
- wherein the storage device and the arithmetic device are mounted on one semiconductor chip.
Dependencies are inferred from the claim text.