Dqs gating in a parallelizer of a memory device

A method, comprising:

• receiving a data strobe at serial register loading circuitry having gating circuitry;
• during a write operation, passing the data strobe through the gating circuitry to a serial shift register;
• passing data from the serial shift register to a data write bus;
• determining whether the write operation has completed;
• and
• upon determining that the write operation has completed, blocking the data strobe from passing from the serial register loading circuitry to the serial shift register to keep the serial shift register from shifting data due to an indeterminate state of the data strobe.

A memory device comprising:

• plurality of memory cells;
• gating circuitry configured to receive a data strobe and to pass the data strobe to a data write bus to capture data to be written in the plurality of memory cells as part of a write operation;
• a data write flip flop configured to receive the data strobe at its clock pin on a last cycle of writing the data in the write operation and to toggle a load signal at its output only on the last cycle of writing the data;
• and
• feedback circuitry configured to feed the load signal back to the gating circuitry to cut off the data strobe from the data write bus after the write operation has been completed.