Techniques for command synchronization in a memory device
AssigneeMicron Technology, Inc.
InventorsYoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
Life of this patent
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Abstract
An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.
Claims22
An apparatus comprising:
- a circuit node configured to receive a clock signal;
- a delay locked loop (DLL) circuit;
- and
- a clock enable control circuit coupled between the circuit node and the DLL circuit and configured to operate in a selected one of first and second states;
- wherein the first state is such that the clock signal is allowed to reach the DLL circuit responsive to issuance of at least one of a read command and a write command, and the second state is such that the clock signal is allowed to reach the DLL circuit earlier than the issuance of any one of the read command and the write command.
An apparatus comprising:
- control circuitry configured to generate a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to place the apparatus in one of a plurality of operational modes;
- a clock enable control circuit configured to receive a read command or the write command (RWD) signal corresponding to a read command or a write command, an active decoded (ACTD) signal corresponding to an activate command, a clock signal and the first control signal, wherein an output of the clock enable control circuit is generated, at least in part, based on a state of the first control signal;
- and
- a timing circuit configured to receive a command signal, the clock signal and the second control signal, wherein an output from the timing circuit is generated, at least in part, based on a state of the second control signal.
A method of operating an apparatus, comprising:
- receiving, at a control circuit, a latency information and delay locked loop (DLL) delay information;
- calculating, at the control circuit, output values of the control circuit, based on the latency information and the DLL delay information;
- and
- setting a mode of operation of the apparatus, based on the output values of the control circuit, and
- wherein the output values of the control circuit indicate whether a DLL circuit achieves a locked condition in response to receipt of read or write commands at a DLL enable control circuit or in response to receipt of activate commands at the DLL enable control circuit.
(canceled)
Dependencies are inferred from the claim text.