Systems and methods for programmable hardware architecture for machine learning
AssigneeCavium, Inc.
InventorsAvinash SODANI, Chia-Hsin CHEN, Ulf R. HANEBUTTE, Hamid Reza GHASEMI, Senad DURAKOVIC
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AssigneeCavium, Inc.
InventorsAvinash SODANI, Chia-Hsin CHEN, Ulf R. HANEBUTTE, Hamid Reza GHASEMI, Senad DURAKOVIC
Estimating the term…
A programmable hardware architecture for machine learning (ML) is proposed, which includes at least a host, a memory, a core, a data streaming engine, a instruction-streaming engine, and an interference engine. The core interprets a plurality of ML commands for a ML operation and/or data received from the host and coordinate activities of the engines based on the data in the received ML commands. The instruction-streaming engine translates the ML commands received from the core and provide a set of programming instructions to the data streaming engine and the inference engines based on the translated parameters. The data steaming engine sends one or more data streams to the inference engine in response to the received programming instructions. The inference engine then processes the data streams received from the data stream engine according to the programming instructions received from the instruction-streaming engine.
A programmable hardware system for machine learning (ML), comprising:
A method to support machine learning (ML) via a programmable hardware system, comprising:
A programmable hardware system for machine learning (ML), comprising:
Dependencies are inferred from the claim text.