Deep learning fpga converter
AssigneeQuanta Computer Inc.
InventorsKuan-Chieh HUANG, Yi-Ting PENG
Life of this patent
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Abstract
Systems and methods for programming field programmable gate array (FPGA) devices are provided. A trained model for a deep learning process is obtained and converted to design abstraction (DA) code defining logic block circuits for programming an FPGA device. Each of these logic block circuits represents one of a plurality of modules that executes a processing step between different layers of the deep learning process.
Claims20
A method, comprising:
- obtaining a trained model for a deep learning process;
- converting the trained model to design abstraction (DA) code;
- programming a field programmable gate array (FPGA) device in a system based on the DA code,
- wherein the DA code comprises code for programming a plurality of logic block circuits in the FPGA device, each of the plurality of logic block circuits representing one of a plurality of modules for executing a processing step between different layers of the deep learning process.
A system, comprising:
- a processor;
- a field programmable gate array (FPGA) communicatively coupled to the processor;
- and
- a memory, having stored therein instructions for causing the processor to perform steps comprising:
- obtaining a trained model for a deep learning process;
- converting the trained model to design abstraction (DA) code;
- and
- programming the FPGA based on the DA code,
- wherein the DA code comprises code for programming a plurality of logic block circuits in the FPGA device, each of the plurality of logic block circuits representing one of a plurality of modules for executing a processing step between different layers of the deep learning process.
A non-transitory computer-readable medium, having stored thereon a computer program executable by a computing device, the computer program comprising a plurality of code sections for causing the computing device to perform steps comprising:
- obtaining a trained model for a deep learning process;
- converting the trained model to a design abstraction (DA) code;
- programming a field programmable gate array (FPGA) device in a system based on the DA code,
- wherein the DA code comprises code for programming a plurality of logic block circuits in the FPGA device, each of the plurality of logic block circuits representing one of a plurality of modules for executing a processing step between different layers of the deep learning process.
Dependencies are inferred from the claim text.