Compilation-time checks to secure processes from speculative rogue cache loads
AssigneeVMware, Inc.
InventorsMichael Wei, Dan Tsafrir, Nadav Amit
Life of this patent
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Abstract
In accordance with embodiments of the present disclosure, a compiler can compile source code to produce binary code that includes address shifting code inserted with memory operations. The address shifting code can shift addresses of memory operations that access locations in the kernel address space into address locations in the user space, thus avoiding speculative access into the kernel address space.
Claims20
A method for generating computer executable machine instructions, the method comprising:
- receiving source code representative of a program expressed in a programming language different from the computer executable machine instructions;
- scanning the source code to generate a plurality of tokens;
- generating intermediate code from the plurality of tokens;
- and
- generating the computer executable machine instructions from the intermediate code, including:
- identifying a plurality of memory operations among the computer executable machine instructions;
- and
- for each memory operation in the plurality of memory operations, inserting address shifting code prior in sequence to that memory operation.
A non-transitory computer-readable storage medium having stored thereon computer executable instructions, which when executed by a computer device, cause the computer device to:
- receive source code representative of a program expressed in a programming language different from the computer executable machine instructions;
- scan the source code to generate a plurality of tokens;
- generate intermediate code from the plurality of tokens;
- and
- generate the computer executable machine instructions from the intermediate code, including:
- identify a plurality of memory operations among the computer executable machine instructions;
- and
- for each memory operation in the plurality of memory operations, insert address shifting code prior in sequence to that memory operation.
An apparatus comprising:
- one or more computer processors;
- and
- a computer-readable storage medium comprising instructions for controlling the one or more computer processors to be operable to:
- receive source code representative of a program expressed in a programming language different from the computer executable machine instructions;
- scan the source code to generate a plurality of tokens;
- generate intermediate code from the plurality of tokens;
- and
- generate the computer executable machine instructions from the intermediate code, including:
- identify a plurality of memory operations among the computer executable machine instructions;
- and
- for each memory operation in the plurality of memory operations, insert address shifting code prior in sequence to that memory operation.
Dependencies are inferred from the claim text.