Systems and methods for creating individualized processing chips and assemblies

A batch of individualized processing chips, wherein each processing chip is arranged to carry out a common processing operation, each individualized processing chip comprising:

• a plurality of logic cells common to the plurality of individualized chips;
• a plurality of interconnects common to the plurality of individualized chips, each interconnect of the plurality of interconnects connecting two or more respective logic cells of the plurality of logic cells;
• a respective set of modifications that implement an individualized set of transformations for the individualized processing chip,
• wherein each transformation of the individualized set of transformations for the individualized processing chip, is a transform for a respective interconnect of the plurality of interconnects,
• wherein the individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.

A system for producing individualized processing chips, each individualized processing chip being arranged to carry out a common processing operation, the system comprising:

• one or more hardware computer processors;
• and
• one or more memories storing machine-readable instructions which, when executed by the one or more hardware processors, cause the one or more hardware processors to:
• receive a processing chip design, wherein the common processing operation is specified, at least in part, by the processing chip design;
• and
• for each individualized processing chip:
• individualize the processing chip design to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations,
• wherein each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design;
• and
• provide the individualized processing chip design for fabrication of the individualized processing chip according to the individualized processing chip design,
• wherein the individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.

A non-transient computer-readable storage medium having instructions embodied thereon, the instructions being executable by one or more processors to perform a method for creating diverse instances of an electronic hardware component, the method comprising:

• receiving a processing chip design, wherein the common processing operation is specified, at least in part, by the processing chip design;
• and
• for each individualized processing chip:
• individualizing the processing chip design to produce an individualized processing chip design, in accordance with an individualized set of transformations for the individualized processing chip, by including a respective set of modifications as part of the individualized processing chip design that implement the individualized set of transformations,
• wherein each transformation of the individualized set of transformations is a transform for an interconnect, specified in the processing chip design, of at least two logic cells specified in the processing chip design;
• and
• providing the individualized processing chip design for fabrication of the individualized processing chip according to the individualized processing chip design,
• wherein the individualized set of transformations for one individualized chip is different to the individualized set of transformations for at least one other individualized chip.