Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization

A computer program product for modifying a manufacturing process for integrated circuits that include memory chips and a memory buffer, the computer program product comprising a non-transitory computer readable storage device having program instructions embodied therewith, the program instructions readable and executable by a computer to perform a method comprising:

• identifying a performance trending estimate of memory chip failures versus memory buffer failures in failed integrated circuits;
• identifying a location and address of each memory chip in the failed integrated circuits that has a memory chip failure;
• identifying a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed;
• predicting a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory chip in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed;
• and
• modifying a manufacturing process for the integrated circuits based on the FA pareto.

A computer system comprising one or more processors, one or more computer readable memories, and one or more computer readable storage mediums, and program instructions stored on at least one of the one or more computer readable storage mediums for execution by at least one of the one or more processors via at least one of the one or more computer readable memories, the stored program instructions comprising:

• program instructions to identify a performance trending estimate of memory integrated circuit failures versus memory buffer failures in failed integrated circuits;
• program instructions to identify a location and address of each memory integrated circuit in the failed integrated circuits that has a memory chip failure;
• program instructions to identify a wafer location on a wafer die on which each memory buffer that has a memory buffer failure was formed;
• program instructions to predict a fault analysis (FA) pareto based on the performance trending estimate, the location and address of each memory integrated circuit in the failed integrated circuits, and the wafer location on the wafer die on which each memory buffer that has the memory buffer failure was formed;
• and
• program instruction to direct a modification of a manufacturing process for the integrated circuits based on the FA pareto.