Coupling aware wire capacitance adjust at global routing

A system for semiconductor chip fabrication comprising:

• a host computing system hosting a capacitance adjust tool and a wire routing tool;
• the capacitance adjust tool hosted by the host computing system performing calculating a ground capacitance adjust for a wire segment going through given routing tiles according to the following operations:
• providing a routing tile having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires;
• computing a plurality of ground capacitance adjusts for the victim wire averaged across a plurality of aggressor slew values to take into account a potential coupling noise effect by neighbors of the victim wire assuming a distribution of signal slews of wires belonging to the routing tile and assuming the victim wire's neighbors have signal slews from the distribution of slews for the routing tile for a plurality of spacing values of single spacing (CASS), double spacing (CADS) and mixed spacing of single and double spacing (CAMS);
• computing a first probability, PSS, that the victim wire will have neighboring wires on the routing tile with those signal slews and located with a single spacing;
• computing a second probability, PDS, that the victim wire will have neighboring wires on the routing tile with those signal slews and located with a double spacing;
• computing a third probability, PMS, that the victim wire will have neighboring wires on the routing tile with those signal slews and located with a mixed spacing;
• computing a first product of the computed ground capacitance adjust for the single spacing multiplied by the first probability;
• computing a second product of the computed ground capacitance adjust for the double spacing multiplied by the second probability;
• computing a third product of the computed ground capacitance adjust for the mixed spacing multiplied by the third probability;
• computing an average value of ground capacitance adjust, CAVS, by summing the first product, second product and the third product;
• repeating for additional wire segments and routing tiles;
• and
• providing the computed average value of ground capacitance adjusts to the wire routing tool;
• the wire routing tool hosted by the host computing system performing the following operations:
• receiving the computed average value of ground capacitance adjusts;
• assigning wires to the routing tiles using the average value of ground capacitance adjusts to avoid coupling nose;
• and
• outputting the placement of the wire segments in the routing tiles to a tool to manufacture a semiconductor chip based on the placement of the wire segments in the routing tiles.

A system for semiconductor chip fabrication, comprising:

• a host computing system hosting a capacitance adjust tool;
• the capacitance adjust tool hosted by the host computing system performing calculating a ground capacitance adjust for a wire segment going through given routing tiles according to the following operations:
• providing a routing tile having a plurality of wires wherein the wire segment being a victim wire and neighboring wires being aggressor wires;
• computing a plurality of ground capacitance adjusts for the victim wire averaged across a plurality of aggressor slew values and across a plurality of spacing values between the victim wire and the neighboring aggressor wires to take into account a potential coupling effect by the neighboring aggressor wires, assuming a distribution of signal slews of wires belonging to the routing tile and assuming the neighboring wires of the victim wire have signal slews from the distribution of slews for the routing tile for the plurality of spacing values responsible for the coupling effect, to guide placement of the wire segment in the routing tile to avoid coupling noise;
• repeating for additional wire segments and routing tiles;
• and
• outputting the placement of the wire segments in the routing tiles to a tool to manufacture a semiconductor chip based on the placement of the wire segments in the routing tiles;
• and
• the tool for manufacturing the semiconductor chip performing the following operations:
• receiving the placement of the wire segments in the routing tiles;
• and
• manufacturing the semiconductor chip based on the placement of the wire segments in the routing tile.