Latch and isolation circuit
Assignee2Pai Semiconductor Co., Limited
InventorZhiwei DONG
Life of this patent
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Assignee2Pai Semiconductor Co., Limited
InventorZhiwei DONG
Estimating the term…
A latch and an isolation circuit are provided. The latch includes a first-level substructure and at least one second-level substructure, the number of the at least one second-level substructure is k, and k is a positive integer greater than or equal to 1. The first-level substructure includes a first load having a first terminal coupled with a first port, a second load having a first terminal coupled with the first port, a first driving circuit having a control terminal coupled with a second terminal of the first load and a second terminal coupled with a second port, a second driving circuit having a control terminal coupled with a second terminal of the second load and a second terminal coupled with the second port. Each of the at least one second-level substructure includes a third load, a fourth load, a third driving circuit and a fourth driving circuit.
A latch, comprising:
Dependencies are inferred from the claim text.