US 2019/0196563 A1Published application

Cost-Effective Clock Structure For Digital Systems And Methods Thereof

AssigneeMediatek Inc.

InventorMing-Shiang Lai

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Abstract

Examples pertaining to a cost-effective clock structure in a digital system are described. When in a low-power mode, a digital circuit operates at a first clock rate, and a counter of a non-stop system timer is incremented using a first clock having the first clock rate. When in a normal mode, the digital circuit operates at a second clock rate greater than the first clock rate, and values of the second clock signal of the second clock between adjacent edges of the first clock signal of the first clock are interpolated using a second clock having the second clock rate. The first clock remains running in both the low-power mode and the normal mode. The second clock is powered down in the low-power mode.

Claims20

Dependent claims

A method, comprising:

determining whether to operate a digital circuit in a low-power mode or a normal mode;
responsive to a determination to operate the digital circuit in the low-power mode, operating the digital circuit at a first clock rate;
and
responsive to a determination to operate the digital circuit in the normal mode, operating the digital circuit at a second clock rate greater than the first clock rate,
wherein the operating of the digital circuit at the first clock rate comprises incrementing a first counter of a non-stop system timer using a first clock having the first clock rate,
wherein the operating of the digital circuit at the second clock rate comprises interpolating, using a second clock having the second clock rate, values of a second clock signal of the second clock between adjacent edges of a first clock signal of the first clock,
wherein the first clock remains running in both the low-power mode and the normal mode, and
wherein the second clock is powered down in the low-power mode.

5 more elements

An apparatus, comprising:

a non-stop system timer comprising a first counter, the non-stop system timer capable of outputting a system timer clock signal based on either a first clock having a first clock rate or a second clock having a second clock rate greater than the first clock rate;
a digital circuit capable to perform digital operations according to the system timer clock signal;
a central processing unit (CPU) capable of controlling the non-stop system timer and the digital circuit to operate either in a low-power mode at the first clock rate or in a normal mode at the second clock rate,
wherein, when in the low-power mode, the non-stop system timer increments the first counter using the first clock,
wherein, when in the normal mode, the non-stop system timer interpolates, using a second clock having the second clock rate, values of a second clock signal of the second clock between adjacent edges of a first clock signal of the first clock,
wherein the first clock remains running in both the low-power mode and the normal mode, and
wherein the second clock is powered down in the low-power mode.

4 more elements

Dependencies are inferred from the claim text.