Image sensor capable of averaging pixel data

An image sensor, comprising:

• a pixel array comprising a first pixel circuit and a second pixel circuit arranged in two columns of a plurality of pixel circuit columns of the pixel array;
• a first readout line configured to output pixel data of the first pixel circuit;
• a first column analog-to-digital converter (CADC) comprising a first comparator, a first detected signal sample capacitor coupled to one input terminal of the first comparator, and a first reference signal sample capacitor coupled to another input terminal of the first comparator;
• a second readout line configured to output pixel data of the second pixel circuit;
• a second CADC comprising a second comparator, a second detected signal sample capacitor coupled to one input terminal of the second comparator, and a second reference signal sample capacitor coupled to another input terminal of the second comparator;
• a first average switch coupled between the one input terminal of the first comparator and the one input terminal of the second comparator;
• and
• a second average switch coupled between the another input terminal of the first comparator and the another input terminal of the second comparator, wherein
• in a first mode, the first average switch and the second average switch are not conducted, and the first CADC and the second CADC are turned on, and
• in a second mode, the first average switch and the second average switch are conducted to average the pixel data on the first readout line and the second readout line, and the second CADC is turned off.

An image sensor, comprising:

• a pixel array comprising a first pixel circuit and a second pixel circuit arranged in two columns of a plurality of pixel circuit columns of the pixel array;
• a first readout line configured to output pixel data of the first pixel circuit;
• a first column analog-to-digital converter (CADC);
• a second readout line configured to output pixel data of the second pixel circuit;
• a second CADC;
• a first storing circuit coupled between the first readout line and the first CADC, and configured to store the pixel data of the first pixel circuit;
• a second storing circuit coupled between the second readout line and the second CADC, and configured to store the pixel data of the second pixel circuit;
• a first bypass path configured to bypass the first storing circuit;
• a second bypass path configured to bypass the second storing circuit;
• and
• at least one average switch coupled between the first storing circuit and the second storing circuit, wherein
• in a first mode, the at least one average switch is not conducted and the first and second bypass paths are conducted, the first CADC is configured to convert the pixel data of the first pixel circuit to digital data, and the second CADC is configured to convert the pixel data of the second pixel circuit to digital data, and
• in a second mode, the at least one average switch is conducted to average the pixel data of the first storing circuit and the second storing circuit, the first and second bypass paths are not conducted and the second CADC is turned off.