Constructing staging trees in hierarchical circuit designs

A system for improving a layout of a clock tree in an integrated circuit, this system comprising:

• one or more computing nodes having a memory and a processor;
• and
• a non-transitory computer readable storage medium of the one or more computing nodes having program instructions embodied therewith, the program instructions executable by the processor to cause the system to:
• receive design data of the integrated circuit, the design data indicating:
• a set of sub-units partitioning an area of the integrated circuit, and
• a clock tree coupling the sub-units, the clock tree having a selected memory element, a predecessor memory element, and successor elements;
• determine a valid placement region for relocating the selected memory element;
• generate grid comprising a first set of perpendicularly intersecting lines through the selected memory element, the predecessor memory element, and the successor elements;
• extend the grid to include a second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines;
• determine, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and to the successor elements;
• and
• relocate the memory element to the determined point.

A computer program product for improving a layout of a clock tree in an integrated circuit, the computer program product including a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processing circuit to cause the processing circuit to perform a method comprising:

• receiving design data of the integrated circuit, the design data indicating:
• a set of sub-units partitioning an area of the integrated circuit, and
• a clock tree coupling the sub-units, the clock tree having a selected memory element, a predecessor memory element, and successor elements;
• determining a valid placement region for relocating the selected memory element;
• generating grid comprising a first set of perpendicularly intersecting lines through the selected memory element, the predecessor memory element, and the successor elements;
• extending the grid to include a second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines;
• determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and to the successor elements;
• and
• relocating the memory element to the determined point.