Super-speed uart with per-frame bit-rate and independent variable upstream and downstream rates

A method performed at a transmitting device comprising:

• generating a transmit clock;
• providing a first transition in a signal transmitted on a transmit line of a universal asynchronous receiver/transmitter (UART) after the transmit line has been idle or after transmitting a first stop bit on the transmit line;
• providing a second transition in the signal, wherein the second transition is provided one-half cycle of the transmit clock after the first transition;
• and
• transmitting a byte of data on the transmit line in accordance with timing provided by the transmit clock.

A clock generator comprising:

• an edge detection circuit configured to detect a negative-transitioning first edge in a receive signal provided to a universal asynchronous receiver/transmitter (UART) receiver circuit, and a positive-transitioning second edge in the receive signal;
• and
• a delay-locked loop (DLL) responsive to the first edge and the second edge, wherein the DLL synchronizes a sampling clock to the first edge and the second edge,
• wherein the sampling clock is used by the UART receiver circuit to capture data from the receive signal.