Phase calibration of clock signals

A receiver with clock phase calibration, the receiver comprising:

• a first sampler configured to sample an input signal according to a first sampling phase that is based on a first clock signal and generate first digital data based on the input signal sampled according to the first sampling phase;
• a first deserializer configured to deserialize the first digital data generated by the first sampler;
• a second sampler configured to sample the input signal according to a second sampling phase that is based on a second clock signal and generate second digital data based on the input signal sampled according to the second sampling phase;
• a second deserializer configured to deserialize the second digital data generated by the second sampler;
• a multiplexor configured to receive the deserialized first digital data generated by the first sampler and the deserialized second digital data generated by the second sampler and select either the deserialized first digital data or the deserialized second digital data as output data by the receiver based on an output selection signal;
• and
• a phase calibration circuit to generate the output selection signal.