Carrier aggregated signal transmission and reception

A radio-frequency integrated chip configured to transmit a carrier aggregated signal, the radio-frequency integrated chip comprising:

• a first carrier transmitter configured to receive a first digital, carrier signal and generate therefrom a first transmitting signal, the first carrier transmitter comprising a first digital mixer configured to translate frequencies of the first digital carrier signal in a digital domain, and a first analog mixer configured to translate frequencies of a first analog Garner signal, derived from the first digital carrier signal, in an analog domain;
• a second carder transmitter configured to receive a second digital earner signal and generate therefrom a second transmitting signal, the second garner transmitter comprising a second digital mixer configured to translate, frequencies of the second digital carrier signal in the digital domain, and a second analog mixer configured to translate frequencies of a second analog carrier signal, derived from the second digital earner signal, in the analog domain;
• and
• a phase-locked loop (PLL) configured to output a first frequency signal having a first frequency to the first carrier transmitter and the second carrier transmitter,
• wherein the first analog mixer up-converts the frequencies of the first analog carrier signal using a second frequency signal generated by dividing the first frequency signal, and the, second analog mixer up-converts the frequencies of the second analog carrier signal using a third frequency signal generated by dividing the first frequency signal.

A wireless communication device configured to receive a receive signal composed of at least first and second carrier signals, the wireless communication device comprising:

• a radio-frequency integrated chip comprising a first carrier receiver configured to receive a first portion of the receive signal and generate therefrom a first digital carrier signal corresponding to the first carrier signal, a second carrier receiver configured to receive a second portion of the receive signal and generate therefrom a second it carrier signal corresponding to the second carrier signal, and a phase-locked loop (PLL) configured to output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver;
• and
• a modulator-demodulator (MODEM) configured to down-convert frequencies of the first digital carrier signal and the second digital carrier signal in a digital domain to provide down-converted first and, second digital carrier signals, and demodulate the first and second down-converted digital carrier signals,
• wherein the first carrier receiver comprises a first analog mixer configured to down-convert frequencies of the receive signal using a second frequency signal generated by dividing the first frequency signal, and the second carrier receiver comprises a second analog mixer configured to down-convert the frequencies of the receive signal using a third frequency signal generated by dividing the first frequency