Analog to digital converters with oversampling
AssigneeAvnera Corporation
InventorsJianping Wen, Ali Hadiashar, Eric King, David Entrikin, Wai Lang Lee
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.
Claims21
1-2. (canceled)
An analog-to-digital modulator for use at the output of an analog device, the analog-to-digital modulator comprising a switched-capacitor loop filter including integrators, the integrators operable in a charging phase using a first clock phase and a dumping phase using a second clock phase non-overlapping with the first clock phase such that during the dumping phase at least some of the integrators are decoupled from the remaining integrators.
An analog-to-digital modulator circuit assembly comprising:
- a switched-capacitor loop filter including integrators configured to operate with a charging phase using a first clock phase and with a dumping phase using a second clock phase, the first clock phase non-overlapping with the second clock phase, the integrators further configured such that at least some of the integrators are decoupled from the remaining integrators during the dumping phase.
A semiconductor die assembly comprising:
- a clock phase generator mounted on the semiconductor die, the clock phase generator configured to generate a first clock phase and a second clock phase, the first clock phase non-overlapping with the second clock phase;
- and
- sa switched-capacitor loop filter mounted on a semiconductor die, the switched-capacitor loop filter including a first set of integrators and a second set of integrators configured to operate in a charging phase driven by the first clock phase and a dumping phase driven by the second clock phase, the first set of decoupled from the second set of integrators during the dumping phase.
Dependencies are inferred from the claim text.