Chopper stabilized comparator for successive approximation register analog to digital converter

A method comprising:

• selectively alternating a polarity of samples of an analog signal to modulate flicker noise;
• comparing, by a comparator in a Successive Approximation Register (SAR) based Analog to Digital Converter (ADC), the samples to reference values to generate digital values;
• demodulating the digital values by selectively inverting the digital values;
• and
• filtering the modulated flicker noise out of the digital values based on modulated flicker noise frequency.

A analog to digital converter (ADC) comprising:

• a Successive Approximation Register (SAR) core sequencer configured to:
• employ chop switches to selectively alternate a polarity of samples of an analog signal to modulate flicker noise prior to comparison to reference values by a SAR comparator to generate digital values;
• and
• employ an un-chop switch to demodulate the digital values by selectively inverting the digital values to support filtering of the modulated flicker noise out of the digital values based on modulated flicker noise frequency.