Multiple via structure for high performance standard cells

A method of operation of a metal oxide semiconductor (MOS) device of an integrated circuit (IC), comprising:

• operating a plurality of p-type MOS (pMOS) transistors, each having a pMOS transistor gate, a pMOS transistor drain, and a pMOS transistor source, each pMOS transistor gate extending in a first direction;
• operating a plurality of n-type MOS (nMOS) transistors, each having an nMOS transistor gate, an nMOS transistor drain, and an nMOS transistor source, each nMOS transistor gate extending in the first direction, each nMOS transistor gate being formed with a corresponding pMOS transistor gate by a same gate interconnect extending in the first direction;
• propagating a first signal through a first metal x (Mx) layer interconnect extending in the first direction and coupling the pMOS transistor drains to the nMOS transistor drains;
• propagating a second signal through a second Mx layer interconnect extending in the first direction and coupling the pMOS transistor drains to the nMOS transistor drains, the second Mx layer interconnect being parallel to the first Mx layer interconnect;
• propagating a third signal through a first metal x+1 (Mx+1) layer interconnect extending in a second direction orthogonal to the first direction, the first Mx+1 layer interconnect being coupled to the first Mx layer interconnect and the second Mx layer interconnect;
• and
• propagating a fourth signal through a second Mx+1 layer interconnect extending in the second direction, the second Mx+1 layer interconnect being coupled to the first Mx layer interconnect and the second Mx layer interconnect, the second Mx+1 layer interconnect being parallel to the first Mx+1 layer interconnect, the first Mx+1 layer interconnect and the second Mx+1 layer interconnect being an output of the MOS device.