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US 2019/0173464 A1Published application
Power unit with an integrated pull-down transistor
AssigneeTexas Instruments Incorporated
InventorsHaian Lin, Frank Alexander Baiocchi, Scott Edward Ragona, Jonathan Almeria Noquil
Life of this patent
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Abstract
One example relates to a circuit that includes a first integrated circuit die and a second integrated circuit die. The first integrated circuit die has a power field effect transistor (FET) and a pull-down FET coupled to the power FET. The second integrated circuit die has a pull-up FET coupled to the power FET.
Claims24
A circuit, comprising:
- a first integrated circuit die including:
- a power field effect transistor (FET);
- and
- a pull-down FET coupled to the power FET;
- and
- a second integrated circuit die having a pull-up FET coupled to the power FET.
3 more elements
A circuit, comprising:
- a first integrated circuit die including:
- a low-side power field effect transistor (FET);
- and
- a low-side pull-down FET coupled to the low-side power FET;
- a second integrated circuit die including:
- a high-side power FET;
- and
- a high-side pull-down FET coupled to the high-side power FET;
- and
- a third integrated circuit die including:
- a low-side pull-up FET that is coupled to the low-side power FET;
- and
- a high-side pull-up FET that is coupled to the high-side power FET.
10 more elements
A circuit, comprising:
- a first integrated circuit die including:
- a low-side power field effect transistor (FET);
- a high-side power FET;
- a low-side pull-down FET coupled to the low-side power FET;
- and
- a high-side pull-down FET coupled to the high-side power FET;
- and
- a second integrated circuit die including:
- a low-side pull-up FET coupled to the low-side power FET;
- and
- a high-side pull-up FET that is coupled to the high-side power FET.
8 more elements
Dependencies are inferred from the claim text.