Utilizing multilayer gate spacer to reduce erosion of semiconductor fin during spacer patterning

A semiconductor device, comprising:

• a gate structure formed over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device;
• and
• a multilayer gate spacer formed on sidewalls of the gate structure;
• wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer;
• wherein the first dielectric layer comprises a dielectric material that has an etch selectivity of about 10:1 or more with respect to the vertical semiconductor fin and the second dielectric layer;
• and
• wherein the second dielectric layer has an etch selectivity of about 10:1 or more with respect to the first dielectric layer.

A semiconductor device, comprising:

• a gate structure formed over a portion of a vertical semiconductor fin of a FinFET (field effect transistor) device;
• and
• a multilayer gate spacer formed on sidewalls of the gate structure;
• wherein the multilayer gate spacer comprises a first dielectric layer and a second dielectric layer;
• wherein the first dielectric layer comprises silicon oxycarbonitride (SiOCN), and wherein the second dielectric layer comprises silicon boron carbon nitride (SiBCN);
• wherein the first dielectric layer has an etch selectivity with respect to materials of the vertical semiconductor fin and the second dielectric layer.