Method of forming vertical transistor having dual bottom spacers
AssigneeInternational Business Machines Corporation
InventorsOleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
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Abstract
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps.
Claims20
A method of forming a spacer for a vertical transistor, the method comprising:
- forming a fin on a substrate;
- depositing a first spacer on the substrate to define gaps between the first spacer and the fin;
- and
- depositing a second spacer in at least the gaps.
A method of forming a spacer for a vertical transistor, the method comprising:
- forming a fin on a substrate;
- depositing a first spacer and an oxide on the fin such that uppermost portions of the first spacer are exposed through the oxide;
- etching portions of the first spacer to re-expose surfaces of the substrate adjacent to the fin via the openings to define gaps between remainders of the first spacer and the fin;
- and
- depositing a second spacer on the re-exposed surfaces of the substrate in at least the gaps.
A method of forming a spacer for a vertical transistor, the method comprising:
- forming multiple fins on a semiconductor substrate;
- depositing a first spacer and an oxide on each of the multiple fins and on exposed surfaces of the semiconductor substrate between and around the multiple fins such that uppermost portions of the first spacer are exposed through openings in the oxide;
- etching portions of the first spacer to re-expose surfaces of the substrate adjacent to each of the multiple fins via the openings to define gaps between remainders of the first spacer and corresponding ones of each of the multiple fins;
- and
- depositing a second spacer on the re-exposed surfaces of the semiconductor substrate in at least the gaps.
Dependencies are inferred from the claim text.