Vertical transport field-effect transistor including air-gap top spacer
AssigneeInternational Business Machines Corporation
InventorsHemanth Jagannathan, Choonghyun Lee, Alexander Reznicek, Christopher Waskiewicz
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Abstract
A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.
Claims20
A method of fabricating a vertical transport field-effect transistor, comprising:
- obtaining a first structure including:
- a vertically extending semiconductor fin including a top region, a bottom region, and a channel region between the top region and the bottom region,
- a bottom source/drain region adjoining the bottom region of the semiconductor fin,
- a gate dielectric layer adjoining the channel region of the semiconductor fin,
- an electrically conductive gate electrode layer adjoining the gate dielectric layer;
- a bottom electrically insulating spacer between the bottom source/drain region and the electrically conductive gate electrode layer, the gate dielectric layer being above the bottom electrically insulating spacer,
- first and second vertically extending dielectric layers;
- a cavity bounded by the first and second vertically extending dielectric layers, the top region of the semiconductor fin extending within the cavity,
- a dielectric liner, the dielectric liner extending horizontally over the gate dielectric layer and the electrically conductive gate electrode layer,
- first and second divots extending downwardly from the cavity and located, respectively, between the top region of the semiconductor fin and the first and second vertically extending dielectric layers, and
- a sacrificial material over the dielectric liner and within the first and second divots;
- removing the sacrificial material;
- and
- epitaxially growing a faceted top source/drain region on the top region of the semiconductor fin and within the cavity such that a top spacer including open gaps is formed between the top source/drain region and the dielectric liner.
A vertical transport field-effect transistor structure, comprising:
- a substrate;
- a semiconductor fin extending vertically with respect to the substrate, the semiconductor fin including a top region, a bottom region, and a channel region between the top region and the bottom region;
- a bottom source/drain region adjoining the bottom region of the semiconductor fin;
- a gate dielectric layer adjoining the channel region of the semiconductor fin;
- an electrically conductive gate electrode layer adjoining the gate dielectric layer;
- a bottom dielectric spacer between the bottom source/drain region and the gate electrode layer;
- first and second vertically extending dielectric layers;
- a cavity bounded by the first and second vertically extending dielectric layers, the top region of the semiconductor fin extending within the cavity;
- first and second divots extending downwardly from the cavity and located between the top region of the semiconductor fin and the first and second vertically extending dielectric layers;
- a faceted, epitaxial top source/drain region on the top region of the semiconductor fin and within the cavity;
- a dielectric liner extending over the gate dielectric layer and the gate electrode layer;
- and
- a top spacer comprising first and second open gaps between the faceted, epitaxial top source/drain region and the dielectric liner.
Dependencies are inferred from the claim text.