Vertical transport field-effect transistor including dual layer top spacer

A method of fabricating vertical transport transistor structures, comprising:

• providing a monolithic structure including:
• a semiconductor substrate,
• first and second parallel semiconductor fins, each of the first and second parallel semiconductor fins including a bottom region adjoining the semiconductor substrate, a top region and a channel region between the bottom region and the top region, and
• a dielectric cap on the top region of each of the first and second semiconductor fins;
• epitaxially growing a bottom source/drain region adjoining the bottom regions of the first and second semiconductor fins directly on a top surface of the semiconductor substrate;
• depositing a bottom electrically insulating spacer over the bottom source/drain region;
• depositing a gate dielectric layer over the bottom electrically insulating spacer and the first and second parallel semiconductor fins;
• depositing a work function metal layer directly on the gate dielectric layer;
• recessing the gate dielectric layer and the work function metal layer, thereby exposing the top regions of the first and second parallel semiconductor fins and top edge portions of the gate dielectric layer;
• depositing an oxidation barrier layer over the work function metal layer, the top regions of the first and second parallel semiconductor fins, the top edge portions of the gate dielectric layer, and the dielectric caps;
• depositing a top dielectric layer over the oxidation barrier layer;
• recessing the oxidation barrier layer and the top dielectric layer, thereby exposing sidewalls of the top regions of the first and second parallel semiconductor fins;
• removing the dielectric caps from the first and second parallel semiconductor fins;
• and
• epitaxially growing first and second top source/drain regions directly on the sidewalls of the top regions of the first and second parallel semiconductor fins such that a portion of the oxidation barrier layer and a portion of the top dielectric layer comprise first and second top spacers positioned respectively between the first and second top source/drain regions and the gate electrode layer.