Vertical transport fets having a gradient threshold voltage

A semiconductor structure comprising:

• a vertical transport nFET and a laterally adjacent vertical transport pFET, wherein
• the vertical transport nFET comprises:
• at least one semiconductor fin present in an nFET device region and extending upwards from a surface of a base semiconductor substrate;
• a bottom n-doped source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom n-doped source/drain structure serves as a drain region;
• a gate dielectric layer located above the bottom n-doped source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
• an nFET gate structure located laterally adjacent a sidewall of the gate dielectric layer, the nFET gate structure comprising a TiN liner having a first threshold voltage and a TiN portion having a second threshold voltage that is greater than the first threshold voltage;
• and
• a top n-doped source/drain structure located on an upper portion of the at least one semiconductor fin and serving a source region;
• and
• the vertical transport pFET comprises:
• at least one semiconductor fin present in a pFET device region and extending upwards from the surface of the base semiconductor substrate;
• a bottom p-doped source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom p-doped source/drain structure serves as a drain region;
• a gate dielectric layer located above the bottom p-doped source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
• a pFET gate structure located laterally adjacent a sidewall of the gate dielectric layer, the pFET gate structure comprising a TiN liner having the second threshold voltage and a TiN portion having a third threshold voltage that is greater than the second threshold voltage;
• and
• a top p-doped source/drain structure located on an upper portion of the at least one semiconductor fin and serving as a source region.