Making electrical components in handle wafers of integrated circuit packages

A fabrication method comprising:

• (a) obtaining a first integrated circuit structure comprising a first substrate comprising a bottom surface having a cavity, and comprising a first circuitry comprising one or more first capacitors each of which is at least partially located in a respective first hole formed in a top surface of the first substrate, each first capacitor comprising:
• a first electroconductive layer formed within or upon an interior surface of the respective first hole;
• a dielectric layer formed over the first electroconductive layer and at least partially located in the respective first hole;
• a second electroconductive layer formed over the dielectric layer and at least partially located in the respective first hole;
• (b) obtaining a second integrated circuit structure comprising a second substrate comprising a second circuitry comprising one or more second capacitors each of which is at least partially located in a respective second hole formed in a top surface of the second substrate, each second capacitor comprising:
• a first electroconductive layer formed within or upon an interior surface of the respective second hole;
• a dielectric layer formed over the first electroconductive layer and at least partially located in the respective second hole;
• a second electroconductive layer formed over the dielectric layer and at least partially located in the respective second hole;
• the second integrated circuit structure further comprising a semiconductor die attached to the top surface of the second substrate and electroconductively coupled to the second circuitry;
• (c) after obtaining the first and second integrated circuit structures, positioning the first and second integrated circuit structures to align each first hole with a corresponding second hole, and bonding the first integrated structure to the second integrated structure, the bonding comprising bonding the first substrate to the second substrate, wherein in said bonding of the first and second integrated structures, for each aligned pair of a first hole and
• a second hole, the first electroconductive layer of the respective first capacitor becomes electroconductively coupled to the second electroconductive layer of the respective second capacitor;
• wherein at a conclusion of said bonding of the first and second integrated circuit structures, the semiconductor die is disposed in the cavity but is spaced from the first substrate to define a headspace between the cavity surface and the semiconductor die surface;
• wherein the method further comprises injecting a filler into the headspace through one or more channels in the first substrate that communicate between the cavity and the top surface of the first substrate.