US 2019/0172846 A1 · METHOD OF FORMING AN INTEGRATED CIRCUIT (IC) WITH SHALLOW TRENCH ISOLATION (STI) REGIONS AND THE RESULTING IC STRUCTURE

Abstract

Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

Claims20

Dependent claims

An integrated circuit structure comprising:

trenches extending vertically through a semiconductor layer, the trenches defining at least one semiconductor mesa;
first sidewall spacers within the trenches positioned laterally adjacent to first sidewalls of the semiconductor mesa;
a device comprising the semiconductor mesa;
and,
a blanket interlayer dielectric layer covering the device and within at least one of the trenches, wherein the first sidewall spacers and the blanket interlayer dielectric layer comprise different dielectric materials.

2 more elements

An integrated circuit structure comprising:

trenches extending vertically through a semiconductor layer, the trenches defining multiple semiconductor mesas;
a liner lining the trenches;
first sidewall spacers within the trenches positioned laterally adjacent to first sidewalls of the semiconductor mesas, wherein the first sidewall spacers are physically separated from the first sidewalls by the liner;
multiple devices comprising at least:
a first semiconductor device comprising a first semiconductor mesa of the semiconductor mesas;
and
a second semiconductor device comprising a second semiconductor mesa of the semiconductor mesas, wherein the first semiconductor device and the second semiconductor device comprise different types of semiconductor devices;
and,
a blanket interlayer dielectric layer over the multiple devices and within at least one of the trenches, wherein the first sidewall spacers and the blanket interlayer dielectric layer comprise different dielectric materials.

6 more elements

An integrated circuit structure comprising:

trenches extending vertically through a semiconductor layer, the trenches defining multiple semiconductor mesas;
an oxide liner lining the trenches;
first sidewall spacers within the trenches positioned laterally adjacent to first sidewalls of each of the semiconductor mesas, wherein the first sidewall spacers are physically separated from the first sidewalls by the oxide liner;
multiple devices comprising at least:
a first semiconductor device comprising a first semiconductor mesa of the semiconductor mesas;
and
a second semiconductor device within one of the trenches above the oxide liner and positioned laterally between adjacent semiconductor mesas;
and,
a blanket interlayer dielectric layer over the multiple devices and within at least one of the trenches, wherein the first sidewall spacers and the blanket interlayer dielectric layer comprise different dielectric materials.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/258,714Filed 28 Jan 2019

Priority

24 Feb 2017

Published

6 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification32 codes

H10D 84/811
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: combinations of…
H10D 1/47
Resistors: resistors having no potential barriers
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 62/151
Source or drain regions of field-effect devices: of igfets

Method of forming an integrated circuit (ic) with shallow trench isolation (sti) regions and the resulting ic structure

Life of this patent

Method of forming an integrated circuit (ic) with shallow trench isolation (sti) regions and the resulting ic structure

Life of this patent

Abstract

Claims20