Semiconductor integrated circuit device
AssigneeSocionext Inc.
InventorKeisuke KISHISHITA
Life of this patent
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Abstract
Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. In a standard cell including nanowire FETs connected in series through an intermediate node used only for mutual connection, the nanowire FETs include first, second, and third pads, Na nanowires extending in an X direction between the first and second pads to connect the first and second pads together, and Nb nanowires extending in the X direction between the second and third pads to connect the second and third pads together.
Claims17
A semiconductor integrated circuit, comprising:
- a standard cell including first and second transistors that are nanowire field effect transistors (FETs), the first and second transistors being connected in series through a connection node used only for mutual connection, wherein
- the first and second transistors include:
- a first pad;
- Na (Na is an integer of one or more) first nanowires each having a first end that is connected to the first pad, each extending in a first direction from the first end, and each having a lower surface above a lower surface of the first pad;
- a first gate electrode surrounding peripheries of the first nanowires within predetermined ranges of the first nanowires in the first direction;
- a second pad connected to second ends of the first nanowires;
- Nb (Nb is an integer of one or more) second nanowires each having a first end that is connected to the second pad, each extending in the first direction from the first end, and each having a lower surface above a lower surface of the second pad;
- a second gate electrode surrounding peripheries of the second nanowires within predetermined ranges of the second nanowires in the first direction;
- and
- a third pad connected to second ends of the second nanowires.
A semiconductor integrated circuit, comprising:
- a standard cell including first and second transistors that are nanowire field effect transistors (FETs),
- wherein
- the first and second transistors include:
- a first pad;
- Na (Na is an integer of one or more) first nanowires each having a first end that is connected to the first pad, each extending in a first direction from the first end, and each having a lower surface above a lower surface of the first pad;
- a first gate electrode surrounding peripheries of the first nanowires within predetermined ranges of the first nanowires in the first direction;
- a second pad connected to second ends of the first nanowires;
- Nb (Nb is an integer of one or more) second nanowires each having a first end that is connected to the second pad, each extending in the first direction from the first end, and each having a lower surface above a lower surface of the second pad;
- a second gate electrode surrounding peripheries of the second nanowires within predetermined ranges of the second nanowires in the first direction;
- and
- a third pad connected to second ends of the second nanowires, and
- the second pad is not connected to any interconnect other than the first and second nanowires.
A semiconductor integrated circuit, comprising:
- a standard cell that is a NAND gate or a NOR gate having a serial portion including M (M is an integer of two or more) nanowire field effect transistors (FETs),
- wherein
- the M nanowire FETs include:
- M+1 pads arranged at a predetermined pitch in a first direction;
- M groups of nanowires each including L (L is an integer of 1 or more) nanowires that are each provided between adjacent ones of the pads, extend in the first direction to connect the adjacent ones of the pads together, and each have a lower surface above lower surfaces of the pads;
- and
- M gate electrodes surrounding peripheries of the associated nanowires within predetermined ranges of the associated nanowires in the first direction.
Dependencies are inferred from the claim text.