Three-dimensional semiconductor memory devices

A three-dimensional (3D) semiconductor memory device comprising:

• a peripheral logic structure comprising a plurality of peripheral logic circuits disposed on a semiconductor substrate;
• a horizontal semiconductor layer disposed on the peripheral logic structure;
• an electrode structure comprising a plurality of electrodes and insulating layers which are vertically and alternately stacked on the horizontal semiconductor layer, the electrode structure having a plurality of recess regions between the insulating layers vertically adjacent to each other;
• a through-insulating pattern penetrating a portion of the electrode structure and a portion of the horizontal semiconductor layer and filling the recess regions of the electrode structure;
• and
• a plurality of through-plugs penetrating the through-insulating pattern and connected to the peripheral logic structure.

A three-dimensional (3D) semiconductor memory device comprising:

• a peripheral logic structure comprising a plurality of peripheral logic circuits disposed on a semiconductor substrate;
• a horizontal semiconductor layer disposed on the peripheral logic structure,
• an electrode structure comprising a plurality of electrodes and insulating layers vertically and alternately stacked on the horizontal semiconductor layer;
• and
• a through-interconnection structure penetrating the electrode structure and the horizontal semiconductor layer and comprising, a through-plug connected to the peripheral logic structure,
• wherein the through-plug is spaced apart from a sidewall of the horizontal semiconductor layer by a first distance, and the first distance is greater than a minimum distance between a sidewall of the electrode structure and the through-plug.