US 2019/0172837 A1 · SEMICONDUCTOR DEVICE

Abstract

To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

Claims10

Dependent claims

1-20. (canceled)

A method of manufacturing a semiconductor device, comprising the steps of:

(a) forming a plurality of first insulating films on a semiconductor substrate in a memory region and forming a plurality of second insulating films on the semiconductor substrate in a capacitive element region,
(b) performing an etching to the semiconductor substrate in a state that the first insulating films and the second insulating films are formed, thereby forming a plurality of first protrusions in the memory region and a plurality of second protrusions in the capacitive element region,
(c) forming a first conductive film via a third insulating film on the first protrusions and on the second protrusions,
(d) forming a plurality of control gate electrodes on the first protrusions and a plurality of first capacitor electrodes on the second protrusions by etching the first conductive film,
(e) forming a second conductive film via a fourth insulating film on the first protrusions and on the second protrusions so as to cover the control gate electrodes and the first capacitor electrodes,
(f) polishing the second conductive film and lowering an upper surface of the second conductive film, and
(g) removing a part of the second conductive film in the memory region, thereby forming a plurality of memory gate electrodes in the memory region such that each of the memory gate electrodes is adjacent to each of the control gate electrodes, and a plurality of second capacitor electrodes in the capacitive element region,
wherein a distance between the adjacent first protrusions is larger than a distance between the adjacent second protrusions.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/269,797Filed 7 Feb 2019

Priority

JP 2017-09025128 Apr 2017

Published

6 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10B 43/40
EEPROM devices comprising charge-trapping gate insulators: characterised by the peripheral circuit region
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10B 43/35
Characterised by the memory core region: with cell select transistors, e.g. NAND
H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims10