Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array
AssigneeMagnaChip Semiconductor, Ltd.
InventorsSu Jin KIM, Hye Jin YOO
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Abstract
A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
Claims10
A method of manufacturing a single poly non-volatile memory device, the method comprising:
- forming a first type lower well by doping first type impurities in a semiconductor substrate;
- forming first and second wells separated in an upper portion of the first type lower well and forming a first type well to enclose each of the first and second wells by doping second type impurities;
- and
- forming a selection transistor and a sensing transistor in an upper portion of the first well and simultaneously forming a control gate in an upper portion of the second well separated on an opposite side of the source electrode from the first well.
A single poly non-volatile memory device array, comprising:
- a cell formed with a selection transistor, a sensing transistor, and a control gate formed in an array form to share a control gate and a source electrode of an adjacent selection transistor,
- wherein program and erase operation voltages are applied to the control gate and the source electrode of the selection transistor.
A single poly non-volatile memory device, comprising:
- a first type lower well;
- first and second wells enclosed in the first type lower well and separated from each other;
- a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in the first well;
- and
- a control gate formed in the second well with separated on an opposite side of the source electrode from the first well and connected to a gate of the sensing transistor,
- wherein program and erase operation voltages are applied to the control gate and the source electrode of the selection transistor.
Dependencies are inferred from the claim text.