Integrated Circuitry And 3D Memory

Three-D (3D) NAND memory circuitry, comprising:

• a stack of tiers of different materials in a memory array circuitry region that comprises a repeating array of elevationally extending strings of memory cells;
• adjacent material in an adjacent circuitry region immediately laterally adjacent to and contacting one elongated major peripheral side of the memory array circuitry region, the adjacent circuitry region being distinct in structure from the memory array circuitry region where contacting the memory array circuitry region and distinct in operation from the memory array circuitry region, the memory array circuitry region and the adjacent circuitry region having a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the memory array circuitry region;
• and
• the stack of tiers of different materials projecting laterally from the memory array circuitry region into the adjacent circuitry region, the adjacent material projecting laterally from the adjacent circuitry region into the memory array circuitry region.

Three-D (3D) NAND memory circuitry, comprising:

• a stack region comprising a stack of tiers of different materials in a memory array circuitry region that comprises a repeating array of elevationally extending strings of memory cells;
• adjacent dielectric material in an adjacent circuitry region immediately laterally adjacent to and contacting one elongated major peripheral side of the memory array circuitry region, the adjacent circuitry region being distinct in structure from the memory array circuitry region where contacting the memory array circuitry region and distinct in operation from the memory array circuitry region, the memory array circuitry region comprising a via region proximate the one elongated major peripheral side of the memory array circuitry region and in which a plurality of conductive vias elevationally extend;
• and
• the tiers of different materials in the stack region being immediately laterally adjacent to and contacting one elongated major peripheral side of the via region, the via region and the stack region having a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the via region.

Three-D (3D) NAND memory circuitry, comprising:

• a stack of tiers of different materials in a memory array circuitry region that comprises a plurality of elevationally extending strings of memory cells and a periphery having a plurality of straight major peripheral sides;
• adjacent material in an adjacent circuitry region that surrounds and contacts each of the straight major peripheral sides of the periphery of the memory array circuitry region;
• and
• the stack of tiers of different materials of the memory array circuitry region and the peripheral circuitry region having a respective longitudinally non-linear edge at an interface relative one another along individual of the straight major peripheral sides of the periphery of the memory array circuitry region circumferentially about the memory array circuitry region.