Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit

A method for protecting an integrated circuit against an electrical conduction assisted by the presence of defects within a dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit, wherein the integrated circuit comprises a plurality of metallization levels including a last metallization level located furthest from a semiconductor substrate, the method comprising:

• etching an encapsulation layer formed above the last metallization level of the interconnection part;
• etching an electrically conducting layer situated above the etched encapsulation layer for the formation of contact pads;
• forming, on the etched electrically conducting layer and on revealed part or parts of the etched encapsulation layer, a stack comprising a non-porous lower passivation layer having a first thickness, an electrically insulating layer having a second thickness and an upper passivation layer having a third thickness, wherein the third thickness is greater than the first thickness;
• and
• locally etching through the stack so as to reveal an upper surface of the contact pads.