Integrated chip scale packages
AssigneeCubic Corporation
InventorJ. Robert Reid
Life of this patent
Estimating the term…
Abstract
Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
Claims27
A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the conductive stub comprises a plurality of sequential layers stacked together as a continuous stack.
(canceled)
A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the dielectric support comprises a first portion embedded in the conductive stub.
A chip scale package, comprising a carrier composed of a plurality of sequential layers stacked together as a continuous stack to provide a monolithic carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create an at least partially hermetic seal at the passageway between the exterior and interior of the carrier, comprising a coaxial connector mounted thereto, the coaxial connector comprising a center conductor electrically connected to the conductive stub and comprising an outer conductor electrically connected to the carrier body to provide a coaxial to coaxial connection.
A method of forming a chip scale package component, comprising:
- depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising:
- a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the conductive stub comprises a plurality of sequential layers stacked together as a continuous stack.
A method of forming a chip scale package component, comprising:
- depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising:
- a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, wherein the dielectric support comprises a first portion embedded in the conductive stub.
A method of forming a chip scale package component, comprising:
- depositing a plurality of layers, wherein the layers comprise one or more of a conductive material and a dielectric material, thereby forming a structure comprising:
- a carrier composed of a plurality of sequential layers of the conductive material stacked together as a continuous stack to provide a monolithic conductive carrier body, the carrier comprising at a selected surface thereof a passageway extending between the exterior and interior of the carrier, the passageway having a conductive stub extending therethrough, the stub suspended in the passageway by a dielectric support, the stub and support cooperating to create a hermetic or partially hermetic seal at the passageway between the exterior and interior of the carrier, comprising mounting a coaxial connector to the carrier, the coaxial connector comprising a center conductor electrically connected to the conductive stub and comprising an outer conductor electrically connected to the carrier body to provide a coaxial to coaxial connection.
(canceled)
Dependencies are inferred from the claim text.