Hybrid high-voltage low-voltage finfet device

A method for fabricating gate dielectric regions for both low-voltage FinFET transistors and hybrid FinFET transistors, the method comprising:

• forming a first layer of first dielectric material over fin structures in both low-voltage FinFET transistors and hybrid FinFET transistors;
• applying a gate masking layer over the first layer of dielectric material for the hybrid FinFET transistors;
• removing the first layer of dielectric material from the fin structures of the low-voltage FinFET transistors;
• removing the hybrid gate masking layer;
• forming a second layer of the first dielectric material over the fin structures in both the low-voltage FinFET transistors and hybrid FinFET transistors;
• and
• forming a layer of a second dielectric layer over the fin structures of all low-voltage and hybrid FinFET transistors.

A method for implanting threshold channel implants for both low-voltage FinFET transistors and hybrid FinFET transistors, the method comprising:

• performing a low-voltage threshold implant in the channel regions of both the low-voltage FinFET transistors and the hybrid FinFET transistors;
• applying an implant masking layer covering the channel regions of the low-voltage FinFET transistors;
• performing a hybrid channel threshold implant in the channel regions of the hybrid FinFET transistors;
• and
• removing the voltage implant masking layer.

A method for implanting threshold channel implants for both low-voltage FinFET transistors and hybrid FinFET transistors, the method comprising:

• performing a low-voltage threshold implant in the channel regions of both the low-voltage n-channel FinFET transistors and the hybrid n-channel FinFET transistors;
• applying an n-channel implant masking layer covering the channel regions of the low-voltage n-channel FinFET transistors;
• performing a hybrid channel threshold implant in the channel regions of the hybrid n-channel FinFET transistors;
• removing the n-channel implant masking layer;
• performing a low-voltage threshold implant in the channel regions of both the low-voltage p-channel FinFET transistors and the hybrid p-channel FinFET transistors;
• applying a p-channel implant masking layer covering the channel regions of the low-voltage p-channel FinFET transistors;
• performing a hybrid channel threshold implant in the channel regions of the hybrid p-channel FinFET transistors;
• and
• removing the p-channel implant masking layer.