High Density, Tight Array Copper Pillar Interconnect Method and Package
AssigneeMicron Technology, Inc.
InventorsOwen R. Fay, Akshay N. Singh, Kyle K. Kirby
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AssigneeMicron Technology, Inc.
InventorsOwen R. Fay, Akshay N. Singh, Kyle K. Kirby
Estimating the term…
A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.
(canceled)
The assembly of claim 9, wherein the conductive material comprises copper.
3-5. (canceled)
The assembly of claim 9, wherein the second substrate comprises a semiconductor device.
The assembly of claim 9, further comprising a third substrate disposed on top of the second substrate, the third substrate having first surface and a second surface opposite the first surface and at least one interconnect between the first surface of the second substrate and the second surface of the third substrate, wherein the at least one interconnect between the second and third substrates is electrically connected to the at least one pillar.
A semiconductor device assembly comprising:
11-26. (canceled)
31-33. (canceled)
A semiconductor device assembly comprising:
42-45. (canceled)
Dependencies are inferred from the claim text.