Three dimensional stacked nonvolatile semiconductor memory

A memory comprising:

• a first memory cell array including a plurality of memory strings, the memory strings including a first memory string and a second memory string,
• the first memory string including a first memory cell transistor and a first select gate transistor, and
• the second memory string including a second memory cell transistor and a second select gate transistor;
• a bit line connected to one end of the first memory string and one end of the second memory string;
• a source line connected to the other end of the first memory string and the other end of the second memory string;
• a first word line connected to a gate of the first memory cell transistor and a gate of the second memory cell transistor;
• a first select gate line connected to a gate of the first select gate transistor;
• and
• a second select gate line connected to a gate of the first select gate transistor,
• wherein when a program operation on the first memory cell transistor is performed,
• a first voltage is applied to the first word line on a first timing,
• a second voltage is applied to the second select gate transistor at the first timing to turn on the second select gate transistor,
• a third voltage is applied to the second select gate transistor at a second timing after the first timing to turn off the second select gate transistor,
• a fourth voltage is applied to the first select gate transistor at a third timing after the second timing to turn on the first select gate transistor, and
• a fifth voltage is applied to the first word line at a fourth timing after the third timing.