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US 2019/0172538 A1Published application
Hybrid memory architectures
AssigneeIntel Corporation
InventorsKumar K. Chinnaswamy, Randy B. OSBORNE, Erik W. Peter
Life of this patent
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Abstract
Methods and apparatuses for providing a hybrid memory module having both volatile and non-volatile memories to replace a DDR channel in a processing system.
Claims20
A system having an integrated circuit (IC) package, the system comprising:
- a processing core disposed within the IC package;
- a volatile memory coupled with the processing core via an internal interface within the IC package, the volatile memory to operate as a last-level hardware managed cache memory;
- a non-volatile memory coupled with the processing core via the internal interface within the IC package, the non-volatile memory to operate as a disk cache;
- a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component.
1 more element
A method comprising:
- receiving a data request;
- searching a cache memory disposed on a die having a processor core generating the data request in response to the data request;
- searching a memory module comprising both volatile and non-volatile memory in response to the requested data not being found in the cache memory, wherein the memory module is external to the die having the processor core generating the data request;
- searching an external memory in response to the requested data not being found in the memory module, wherein the memory module is external to the die having the processor core generating the data request and the memory module.
1 more element
A processing system having comprising:
- a processing core disposed within a first IC package;
- a volatile memory disposed within a second IC package, the volatile memory coupled with the processing core via an interface between the first IC package and the second IC package, the volatile memory to operate as a last-level hardware managed cache memory;
- a non-volatile memory disposed within the second IC package, the non-volatile memory coupled with the processing core via the interface between the first IC package and the second IC package, the non-volatile memory to operate as a disk cache;
- a memory interface coupled with the processing core, the memory interface to provide a communication interface to an external memory component.
1 more element
Dependencies are inferred from the claim text.