Solid state drive architectures
AssigneeThstyme Bermuda Limited
InventorsCharles I. Peddle, Martin Snelgrove, Robert Neil McKenzie, Xavier Snelgrove
Life of this patent
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Abstract
A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.
Claims20
A solid state drive (SSD) comprising:
- dynamic random access memory (DRAM);
- flash memory;
- a solid state drive (SSD) controller;
- and
- a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM,
- wherein the SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.
A method, comprising:
- receiving from a computing device, a command to access a solid state drive (SSD), wherein the command includes a logical block address and a command word;
- storing the command in a command block of an SSD controller;
- determining, from a logical record (LR) table stored in a memory manager of the SSD controller, whether the logical block address maps to a pointer to a location on dynamic random access memory (DRAM);
- and
- when the logical block address maps to a pointer in the DRAM, executing the command in the DRAM based on the mapping, while preventing access of the computing device to flash memory of the SSD.
A solid state drive (SSD) comprising:
- dynamic random access memory (DRAM);
- flash memory comprising:
- multiple flash die;
- at least one flash interface controller to buffer data to be written to a subset of the multiple flash die from the DRAM;
- and
- a flash controller per flash interface controller and paired with a flash die to manage data access into and out of the flash die,
- a peripheral component interconnect express (PCIe) bus coupling the SSD to a computing device;
- and
- a solid state drive (SSD) controller comprising:
- a non-volatile memory express (NVMe) controller to receive commands to access the SSD;
- a command block to receive and store the commands, wherein a command includes a logical block address and a command word;
- a memory manager to manage data transfer into and out of the DRAM based on a mapping between the logical block address of the command and a pointer to a location in the DRAM;
- a logical flash controller to manage data transfer between the SSD and the computing device;
- wherein less than all writes to the SSD are written to the flash memory.
Dependencies are inferred from the claim text.