Resistive memory cell programmed by metal alloy formation and method of operating thereof

A method of operating an array of resistive memory cells, comprising:

• providing an array of resistive memory cells, wherein each resistive memory cell within the array comprises a barrier material layer containing at least one of silicon or germanium electrically connected to a respective first electrode, and a metal oxide layer including an oxide of a metal element that provides a reversible chemical reaction under a bidirectional electrical bias at an interface with the barrier material layer electrically connected to a respective second electrode, wherein the reversible chemical reaction is selected from silicidation reaction between the barrier material layer and the metal element, germanidation reaction between the barrier material layer and the metal element, oxidation of the metal element, and reduction of the metal element;
• performing a reset operation that induces a high resistance state on a first plurality of resistive memory cells within the array at least by applying a positive bias voltage pulse to the respective second electrode relative to the respective first electrode;
• performing a set operation that induces a low resistance state on a second plurality of resistive memory cells within the array at least by applying a negative bias voltage pulse to the respective second electrode relative to the respective first electrode;
• selecting a subset of resistive memory cells having a resistance that is lower than a predetermined minimum reset resistance after applying a respective positive bias voltage pulse to a respective second electrode;
• applying a positive corrective bias voltage pulse to the respective second electrode at least once during each reset operation for each resistive memory cell within the selected subset of resistive memory cells, wherein the positive corrective bias voltage pulse is applied to the second electrode multiple times for each resistive memory cell within the selected subset:
• measuring the resistance of the memory cell after each application of the positive corrective bias voltage for each resistive memory cell within the selected subset;
• determining an incremental increase in the resistance of the memory cell for each measured value of the resistance of the memory cell relative an immediately preceding measured value of the resistance of the memory cell for each resistive memory cell within the selected subset;
• determining whether the incremental increase in resistance is less than a predetermined threshold for incremental increase in resistance after each application of the positive corrective bias voltage pulse for each resistive memory cell within the selected subset:
• determining whether resistance as measured after application of the positive corrective bias voltage is greater than a minimum reset resistance for each resistive memory cell within the selected subset;
• and
• discontinuing application of the positive corrective bias voltage if the incremental increase in resistance is less than a predetermined threshold for incremental increase in resistance and if the resistance as measured after application of the positive corrective bias voltage is greater than a minimum reset resistance for each resistive memory cell within the selected subset,
• wherein at least one of an absolute value of amplitude and duration of the positive bias voltage pulses employed during the reset operation is greater than that employed during the set operation.

A method of operating an array of resistive memory cells, comprising:

• providing an array of resistive memory cells, wherein each resistive memory cell within the array comprises a barrier material layer containing at least one of silicon or germanium electrically connected to a respective first electrode, and a metal oxide layer including an oxide of a metal element that provides a reversible chemical reaction under a bidirectional electrical bias at an interface with the barrier material layer electrically connected to a respective second electrode, wherein the reversible chemical reaction is selected from silicidation reaction between the barrier material layer and the metal element, germanidation reaction between the barrier material layer and the metal element, oxidation of the metal element, and reduction of the metal element;
• performing a reset operation that induces a high resistance state on a first plurality of resistive memory cells within the array at least by applying a positive bias voltage pulse to the respective second electrode relative to the respective first electrode;
• performing a set operation that induces a low resistance state on a second plurality of resistive memory cells within the array at least by applying a negative bias voltage pulse to the respective second electrode relative to the respective first electrode;
• selecting a subset of resistive memory cells having a resistance that is higher than a predetermined maximum set resistance after applying a respective negative bias voltage pulse to a respective second electrode;
• applying a negative corrective bias voltage pulse to the respective second electrode at least once during each set operation for each resistive memory cell within the selected subset, wherein the negative corrective bias voltage pulse is applied to the second electrode multiple times for each resistive memory cell within the selected subset;
• measuring the resistance of the memory cell after each application of the negative corrective bias voltage for each resistive memory cell within the selected subset;
• determining an incremental decrease in the resistance of the memory cell for each measured value of the resistance of the memory cell relative an immediately preceding measured value of the resistance of the memory cell for each resistive memory cell within the selected subset of resistive memory cells;
• determining whether the incremental decrease in resistance is less than a predetermined threshold for incremental decrease in resistance after each application of the positive corrective bias voltage pulse for each resistive memory cell within the selected subset;
• determining whether resistance as measured after application of the negative corrective bias voltage is less than a maximum set resistance for each resistive memory cell within the selected subset;
• and
• discontinuing application of the positive corrective bias voltage if the incremental decrease in resistance is less than a predetermined threshold for incremental decrease in resistance and if the resistance as measured after application of the negative corrective bias voltage is less than a maximum set resistance for each resistive memory cell within the selected subset,
• wherein at least one of an absolute value of amplitude and duration of the positive bias voltage pulses employed during the reset operation is greater than that employed during the set operation.

A method of operating an array of resistive memory cells, comprising:

• providing an array of resistive memory cells, wherein each resistive memory cell within the array comprises a barrier material layer containing at least one of silicon or germanium electrically connected to a respective first electrode, and a metal oxide layer including an oxide of a metal element that provides a reversible chemical reaction under a bidirectional electrical bias at an interface with the barrier material layer electrically connected to a respective second electrode, wherein the reversible chemical reaction is selected from silicidation reaction between the barrier material layer and the metal element, germanidation reaction between the barrier material layer and the metal element, oxidation of the metal element, and reduction of the metal element;
• performing a reset operation that induces a high resistance state on a first plurality of resistive memory cells within the array at least by applying a positive bias voltage pulse to the respective second electrode relative to the respective first electrode;
• performing a set operation that induces a low resistance state on a second plurality of resistive memory cells within the array at least by applying a negative bias voltage pulse to the respective second electrode relative to the respective first electrode;
• and
• performing an initializing reset operation selected from at least one of:
• performing the initializing reset operation on at least some resistive memory cells in the array that are not in active use for storage of data in a background operation while a subset of the array is employed to store data;
• or
• periodically performing the initializing reset operation on each resistive memory cell within the array at a predetermined time interval that is in a range from 1 hour to 336 hours,
• wherein at least one of an absolute value of amplitude and duration of the positive bias voltage pulses employed during the reset operation is greater than that employed during the set operation.