High Density Split-Gate Memory Cell

A memory device, comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;
• each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
• first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions,
• a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region,
• a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region,
• an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions,
• a first coupling gate disposed over and insulated from the first floating gate, and
• a second coupling gate disposed over and insulated from the second floating gate;
• control circuitry configured to program one of the pairs of memory cells by applying to the one pair of memory cells:
• a first positive voltage to the first region,
• a current to the second region,
• a second positive voltage to the first coupling gate,
• a third positive voltage to the second coupling gate, and
• a fourth positive voltage to the erase gate.

A memory device, comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;
• each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
• first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions,
• a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region,
• a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region,
• an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions,
• a first coupling gate disposed over and insulated from the first floating gate, and
• a second coupling gate disposed over and insulated from the second floating gate;
• control circuitry configured to erase one of the pairs of memory cells by applying to the one pair of memory cells:
• a zero voltage to the first region,
• a zero voltage to the second region,
• a first negative voltage to the first coupling gate,
• a second negative voltage to the second coupling gate, and
• a positive voltage to the erase gate.

A memory device, comprising:

• a substrate of semiconductor material of a first conductivity type;
• spaced apart isolation regions formed on the substrate which are substantially parallel to one another and extend in a first direction, with an active region between each pair of adjacent isolation regions also extending in the first direction;
• each of the active regions including a plurality of pairs of memory cells, each of the memory cell pairs includes:
• first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a continuous channel region in the substrate extending between the first and second regions,
• a first floating gate disposed over and insulated from a first portion of the channel region adjacent to the first region,
• a second floating gate disposed over and insulated from a second portion of the channel region adjacent to the second region,
• an erase gate disposed over and insulated from a third portion of the channel region between the first and second channel region portions,
• a first coupling gate disposed over and insulated from the first floating gate, and
• a second coupling gate disposed over and insulated from the second floating gate;
• control circuitry configured to erase one memory cell of a pair of memory cells by applying to the one pair of memory cells:
• a zero voltage to the first region,
• a zero voltage to the second region,
• a first negative voltage to the first coupling gate,
• a zero or positive voltage to the second coupling gate, and
• a positive voltage to the erase gate.