Sram memory having a fast clear

Static random access memory device comprising a memory matrix provided with at least one column formed from a plurality of SRAM memory cells, each of said cells comprising:

• a first logical information storage node and a second complementary logical information storage node,
• a first access transistor to the first storage node and a second access transistor to the second storage node, the first access transistor and the second access transistor being connected to a first bit line and a second bit line respectively, the first bit line and the second bit line being shared by said cells of said column,
• the device also comprising an erase memory circuit configured to force conduction of the access transistors of said cells and to connect said first bit line and said second bit line to each other, following reception of an erase signal.