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US 2019/0172522 A1Published application
SRAM Configuration Cell for Low-Power Field Programmable Gate Arrays
AssigneeMicrosemi SoC Corporation
InventorsJonathan W. Greene, John McCollum
Life of this patent
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Abstract
A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
Claims12
A random-access memory cell comprising:
- first and second voltage supply nodes;
- first and second complementary output nodes;
- first and second complementary bit lines associated with the memory cell;
- a word line associated with the memory cell;
- a first pair of series-connected p-channel hybrid FinFET transistors connected between the first power supply node and the first output node;
- a first pair of series-connected n-channel hybrid FinFET transistors connected between the first output node and the second power supply node;
- a second pair of series-connected p-channel hybrid FinFET transistors connected between the first power supply node and the first output node;
- a second pair of series-connected n-channel hybrid FinFET transistors connected between the first output node and the second power supply node;
- gates of the first pair of series-connected p-channel hybrid FinFET transistors and the first pair of series-connected n-channel hybrid FinFET transistors connected to the second output node;
- gates of the second pair of series-connected p-channel hybrid FinFET transistors and the second pair of series-connected n-channel hybrid FinFET transistors connected to the first output node;
- the first bit line coupled to the first output node, and
- the second bit line coupled to the second output node.
9 more elements
A static random-access memory cell comprising:
- first and second voltage supply nodes;
- first and second complementary output nodes;
- first and second complementary bit lines associated with the memory cell;
- a word line associated with the memory cell;
- a first pair of series-connected p-channel hybrid FinFET transistors connected between the first voltage supply node and the first output node;
- a first pair of series-connected n-channel hybrid FinFET transistors connected between the second voltage supply node and the first output node;
- a second pair of series-connected p-channel hybrid FinFET transistors connected between the first voltage supply node and the second output node;
- a second pair of series-connected n-channel hybrid FinFET transistors connected between the second voltage supply node and the second output node;
- the first pair of series-connected p-channel hybrid FinFET transistors and the first pair of series-connected n-channel hybrid FinFET transistors each having gates connected together to the second output node, and the second pair of series-connected p -channel hybrid FinFET transistors and the second pair of series-connected n-channel hybrid FinFET transistors each having gates connected together to the second output node;
- an n-channel hybrid FinFET transistor switch having a gate connected to one of the first and second output nodes;
- a first n-channel hybrid FinFET select transistor coupled between the first bit line and the first output node;
- a second n-channel hybrid FinFET select transistor coupled between the second bit line and the second output node;
- and
- the first and second n-channel hybrid FinFET select transistors each having a gate coupled to the word line.
11 more elements
A method of operating a random-access memory cell formed from pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors coupled to a pair of complementary bit lines through a pair of hybrid FinFET select transistors, the method comprising:
- during a programming mode of operation powering the memory cell with a first voltage potential and placing one of the first potential and 0V on a first one of the bit lines and the other one of the first potential and 0V on a second one of the bit lines;
- and
- during a read mode of operation powering the memory cell with a second voltage potential higher than the first voltage potential and placing half of the second voltage potential on both of the complementary bit lines.
An integrated circuit comprising:
- a plurality of first random-access memory cells each including first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with each first memory cell, and a word line associated with each first memory cell, each first memory cell further including pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node;
- and
- a plurality of second random-access memory cells each including first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with each second memory cell, and a word line associated with each second memory cell, each second memory cell further including cross-coupled p-channel and n-channel hybrid FinFET transistors connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
Dependencies are inferred from the claim text.