Gate Driver and Display Device Including the Same

A gate driver comprising:

• a plurality of stages,
• wherein each stage includes:
• a transistor T6 configured to output an emission signal of a gate-on voltage to a node Na while a node Q is activated;
• a transistor T7 configured to output the emission signal of a gate-off voltage to the node Na while a node QB is activated;
• a Q controller configured to control a voltage of the node Q depending on a voltage of a node Q′ and a clock signal ECLK1 and a clock signal ECLK2 which are in antiphase;
• a QB controller configured to control a voltage of the node QB depending on the clock signal ECLK1, the voltage of the node Q, and the voltage of the node Q′;
• and
• a capacitor CQ connected between an input terminal of the clock signal ECLK1 and the node Q and having a first capacitance,
• wherein a ratio of the first capacitance to a total capacitance including the first capacitance and a parasitic capacitance formed in the node Q is 50% or more.