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US 2019/0171815 A1Published application
Multi-Level Distributed Pattern Processor
AssigneeHangZhou HaiCun Information Technology Co., Ltd.
InventorGuobiao ZHANG
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Abstract
A multi-level distributed pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a non-volatile memory (NVM) array and a pattern-processing circuit. The NVM array and the pattern-processing circuit are disposed on different physical levels.
Claims20
A pattern processor, comprising an input bus for transferring at least first data related to a first pattern;
- and, a plurality of storage-processing units (SPU's) communicatively coupled with said input bus, each of said SPUs comprising:
- at least a non-volatile memory (NVM) array for storing at least second data related to a second pattern, wherein said NVM array is not a random-access memory (RAM);
- a pattern-processing circuit for performing pattern processing for said first and second patterns;
- and
- inter-level connections for communicatively coupling said NVM array and said pattern-processing circuit;
- wherein said NVM array and said pattern-processing circuit are disposed on different physical levels.
3 more elements
A pattern processor, comprising an input bus for transferring at least first data related to a search pattern;
- and, a plurality of storage-processing units (SPU) communicatively coupled with said input bus, each of said SPUs comprising:
- at least a non-volatile memory (NVM) array for storing at least second data related to a target pattern, wherein said NVM array is not a random-access memory;
- a pattern-processing circuit for performing pattern processing for said search and target patterns;
- and
- electrical connections for communicatively coupling said NVM array and said pattern-processing circuit.
2 more elements
Dependencies are inferred from the claim text.