Integrated circuit structure

A semiconductor structure comprising:

• a first device region extending from a first power rail to a second power rail, the first device region containing an entirety of a first active area of a first logic device;
• a second device region extending from the first power rail to the second power rail, the second device region containing an entirety of a second active area of a second logic device, wherein the first device region and the second device region share a boundary extending from the first power rail to the second power rail;
• a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary between the first active area and the second active area;
• and
• a via contacting the first metal zero pin, wherein a distance from the center of the via to the boundary is less than or equal to a first predetermined distance based on a metal zero minimum via enclosure length,
• wherein the via is electrically connected to one of the first active area or the second active area.

A semiconductor structure comprising:

• a first logic device positioned between a first power rail and a second power rail, the first logic device comprising a first active area;
• a second logic device positioned between the first power rail and the second power rail, the second logic device comprising a second active area aligned with the first active area along a first direction parallel to the first power rail and the second power rail;
• a metal pin extending in the first direction and overlying one of the first active area or the second active area;
• and
• a plurality of metal wires extending in a second direction perpendicular to the first direction and having a metal wire pitch,
• wherein
• a first metal wire of the plurality of metal wires overlies the metal pin and is electrically connected to the one of the first active area or the second active area through the metal pin,
• a second metal wire of the plurality of metal wires is adjacent to the first metal wire of the plurality of metal wires, overlies the first active area, and is electrically connected to the first logic device, and
• a third metal wire of the plurality of metal wires is adjacent to the first metal wire of the plurality of metal wires, overlies the second active area, and is electrically connected to the second logic device.