Superconducting quantum circuits layout design verification

A computer program product for verifying a quantum circuit layout design, the computer program product comprising a computer readable tangible storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method, comprising:

• performing design rules checking on the qubit layout input, using a predefined set of design rules;
• extracting bus style/frequency and qubit information from the qubit layout input;
• automatically generating a new qubit schematic from the extracted bus style/frequency and qubit information;
• and
• verifying the qubit layout, based on the new qubit schematic being the same as the qubit schematic.

A computer system for verifying a quantum circuit layout design, the computer system comprising:

• a computer readable storage device having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to cause the processor to perform a method comprising:
• receiving a qubit layout input generated from a qubit schematic, wherein the qubit schematic includes a plurality of qubits, a plurality of coupling buses, a plurality of readout buses, and a plurality of readout ports;
• performing design rules checking on the qubit layout input, using a predefined set of design rules;
• extracting bus style/frequency and qubit information from the qubit layout input;
• automatically generating a new qubit schematic from the extracted bus style/frequency and qubit information;
• and
• verifying the qubit layout, based on the new qubit schematic being the same as the qubit schematic.