Systems and methods for top level integrated circuit design

A non-transitory computer-readable medium storing instructions which, when executed, causing one or more processors to perform a computerized method for designing top level integrated circuits, the method comprising:

• receiving register transfer level (RTL) descriptions of an integrated circuit device;
• generating generic physical descriptions of components and connectivity, based on the RTL descriptions;
• grouping the component descriptions into blocks;
• analyzing the connectivity of the components descriptions;
• based on the analysis, identifying components in the blocks, which can be removed with no effect on TOP level design;
• removing RTL descriptions of the removable components from the blocks;
• converting RTL descriptions remaining after the removal into gate level descriptions by synthesis process;
• and
• specifying placement regions and routing blockages.

A system for IC Top level physical design, comprising:

• a memory device;
• an input unit;
• an output unit;
• and
• a processing unit, executing the instructions to:
• receive register transfer level (RTL) descriptions of an integrated circuit device;
• generate generic physical descriptions of components and connectivity, based on the RTL descriptions;
• group the component descriptions into blocks;
• analyze the connectivity of the components descriptions;
• based on the analysis, identify components in the blocks, which can be removed with no effect on TOP level design;
• remove RTL descriptions of the removable components from the blocks;
• convert RTL descriptions remaining after the removal into gate level descriptions by synthesis process;
• and
• specify placement regions and routing blockages.