Protocol-framed clock line driving for device communication over master-originated clock line

An apparatus adapted for communicating over a serial bus comprising:

• a processor configured to provide an alert code for transmission on a first line of the serial bus while data is transmitted by another device on a second line of the serial bus;
• and
• an interface circuit adapted to couple the apparatus to the serial bus, wherein the interface circuit comprises:
• a line driver coupled to the first line of the serial bus, wherein the data is transmitted on the second line of the serial bus in accordance with timing provided by a clock signal received from the first line of the serial bus, and
• wherein the interface circuit is configured to:
• detect that the clock signal has transitioned from a first signaling state to a second signaling state while the data is being transmitted on the second line;
• activate the line driver after the first line of the serial bus has transitioned from the first signaling state to the second signaling state when a first bit of the alert code has a first value;
• drive the first line of the serial bus to the first signaling state to transmit a first bit of data when the first bit of the alert code has the first value;
• and
• refrain from driving the first line when the first bit of the alert code has a second value.

A method implemented at a first device coupled to a serial bus, the method comprising:

• participating in a transaction with a second device coupled to the serial bus in which a first datagram is transmitted on a first line of the serial bus in accordance with a clock signal transmitted by a master device on a second line of the serial bus;
• and
• transmitting a second datagram by pulse width modulating the clock signal while the first datagram is being transmitted, wherein a bit of the second datagram is encoded in the clock signal by:
• detecting a first edge in the clock signal, wherein the master device is configured to enter a high impedance state with respect to the second line after driving the first edge;
• driving the second line to generate a second edge in the clock signal when the bit has a first value;
• and
• refraining from driving the second line when the bit has a second value.

An apparatus operable for transmitting data over a serial bus comprising:

• a bus interface configured to couple the apparatus to the serial bus, the bus interface including a line driver adapted to drive a first line of the serial bus;
• and
• a controller configured to:
• participate in a transaction with another device coupled to the serial bus in which a first datagram is transmitted on the first line of the serial bus in accordance with a clock signal transmitted by a master device on a second line of the serial bus;
• and
• cause the bus interface to pulse width modulate each bit of a second datagram by:
• detecting a first edge in the clock signal, wherein the master device is configured to enter a high impedance state with respect to the second line after driving the first edge;
• driving the second line to generate a second edge in the clock signal when the bit has a first value;
• and
• refraining from driving the second line when the bit has a second value.